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Research Article | Open Access
Volume 8 | Issue 1 | Year 2021 | Article Id. IJVSP-V8I1P103 | DOI : https://doi.org/10.14445/23942584/IJVSP-V8I1P103

Tiling Based Concurrent Supervision of Power And Fault Tolerance In Heterogeneous Multicore Embedded Systems

S.Murugalakshmi, Dr. P.Ranjith Kumar

Citation :

S.Murugalakshmi, Dr. P.Ranjith Kumar, "Tiling Based Concurrent Supervision of Power And Fault Tolerance In Heterogeneous Multicore Embedded Systems," International Journal of VLSI & Signal Processing, vol. 8, no. 1, pp. 10-13, 2021. Crossref, https://doi.org/10.14445/23942584/IJVSP-V8I1P103

Abstract

Increasing power densities had led to the dark silicon era, for which miscellaneous multicores with various power and performance characteristics are promising architectures. In this system, peak-power-aware reliability management (PPARM) is presented with a power density for reliability constraints. To balance the reliability issue, we also employ a tiling-based prohibitions method to further diminish the consumption of power. This system has resulted in an average of less peak and low area consumption.

Keywords

PPARM, Tiling, reliability

References

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