SPI Controller Core: Verification

Nidhi Gopal

doi:https://doi.org/10.14445/23942584/IJVSP-V2I5P101

Research Article | Open Access

Volume 2 | Issue 3 | Year 2015 | Article Id. IJVSP-V2I3P101 | DOI : https://doi.org/10.14445/23942584/IJVSP-V2I5P101

SPI Controller Core: Verification

Nidhi Gopal

Citation :

Nidhi Gopal, "SPI Controller Core: Verification," International Journal of VLSI & Signal Processing, vol. 2, no. 3, pp. 1-6, 2015. Crossref, https://doi.org/10.14445/23942584/IJVSP-V2I5P101

Abstract

This paper mainly deals with the study of Serial Peripheral Interface and logical Implementation through RTL, Synthesis and Simulation by making Test benches of various modules involved using Universal Verification Methodology. It is done with the help of Questasim 10.0b software. Further, output in both Batch and GUI Mode has been observed and discussed. Various test cases of SPI Protocol are taken into consideration, functional coverage, code coverage, and assertion coverage has been verified by synthesis of various blocks involved in top level architecture of SPI.

Keywords

Questasim, RTL, SPI, Synthesis, Simulation, Testcases.

References

[1]. Prof Jai Karan Singh, prof Mukesh Tiwari, Karan Sharma;”Implementation of SPI SLAVE on FPGA”; International Journal of Advanced Engineering and technology; Volume :20
[2]. T. Durga Prasad, B. Ramesh Babu; Design and Simulation of SPI Master / Slave UsingVerilog HDL; International Journal of Science and Research.; Volume:03, Issue:08, August 2014.
[3]. Google; Wikipedia.
[4]. Maven Silicon Study Material.
[5] Arunadevi A. ,Chitra K., GunaNandhini S., Raghupathi T., Rejusha M; “A Review on Area Efficient Parallel FIR Digital Filter Implementation”;Volume:02, Issue:02, SSRG-IJVSP, March-April 2015.
[6] Shilpi Thawait, Jagveer Verma;” FPGA Implementation of Simple and High Speed Vedic Multiplier”; Volume:02; Issue:03, SSRG-IJVSP,May-June 2015.