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Research Article | Open Access
Volume 6 | Issue 7 | Year 2019 | Article Id. IJEEE-V6I7P101 | DOI : https://doi.org/10.14445/23488379/IJEEE-V6I7P101

ASIC Design Flow And Methodology – An Overview

Ashish A Shetty

Citation :

Ashish A Shetty, "ASIC Design Flow And Methodology – An Overview," International Journal of Electrical and Electronics Engineering, vol. 6, no. 7, pp. 1-5, 2019. Crossref, https://doi.org/10.14445/23488379/IJEEE-V6I7P101

Abstract

ASICs are complex. Can contain more than millions of transistors which makes it impossible to do the entire design at one level of abstraction - say through the schematic entry or through custom layout! The individual engineers will be having limited roles with in one sub domain of a VLSI Design and not aware of how their part of work is relevant. A very few people will be having over view of the entire sub domains of VLSI Design – from RTL to GDS. This paper attempts to connect each subdomain with other VLSI Design subdomains, explain how they interact each other. Though GPPs and ASPPs designed and manufactured with similar Methodologies, this paper will focus more on ASIC Design Methodologies.

Keywords

VLSI, ASIC Design, ASIC Design Methodology, Semicustom Design Methodology, Full Custom Design Methodology, FPGA Design Methodology.

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