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Research Article | Open Access
Volume 12 | Issue 7 | Year 2025 | Article Id. IJEEE-V12I7P119 | DOI : https://doi.org/10.14445/23488379/IJEEE-V12I7P119

Fast and Low Power Implementation of Ternary ALU

Nagarathna, Srividya B V, Soumya S, Deepti Raj, Vinod B Durdi

Citation :

Nagarathna, Srividya B V, Soumya S, Deepti Raj, Vinod B Durdi, "Fast and Low Power Implementation of Ternary ALU," International Journal of Electrical and Electronics Engineering, vol. 12, no. 7, pp. 264-273, 2025. Crossref, https://doi.org/10.14445/23488379/IJEEE-V12I7P119

Abstract

A ternary ALU is an Arithmetic Logic Unit (ALU) that operates in a ternary (base-3) number system as opposed to the traditional binary (base-2) number system. In contrast to a binary ALU, which only processes 0s and 1s, a ternary ALU (Trit rather than bit) processes three possible values per digit. Every Trit contains more than a bit of information. For some ternary processes, utilizing fewer logic gates can reduce energy consumption. Trits represent the values of 0, 1, or 2 (an imbalanced ternary), making them efficient. A ternary ALU performs arithmetic and logical operations using ternary logic gates and ternary arithmetic circuits. The Ternary ALU is designed using forced-stack multi-threshold MOSFETS. On five-digit ternary data, operations like addition, subtraction, multiplication, and Trit-wise AND, OR, NAND, NOR, XOR, and NOT are carried out. To guarantee the least amount of energy usage, power analysis is done. Nevertheless, it only consumes 81.4% of the power, proving the effectiveness of low-power design techniques. Also, comparing ternary multipliers to binary multipliers, the performance analysis reveals a switching speed gain of roughly 5.35%. Cadence Virtuoso is used in the design and implementation of the ternary logic gates and circuits using 45nm technology.

Keywords

Low power, Forced Stack Multi Threshold Transistors (FSMT), Ternary, Decoder, Logic Gates, Arithmetic Unit, Logic Unit.

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