Design of Low Power Encoder Using Switch Logic

Shaik Hameeda Noor

doi:https://doi.org/10.14445/23488549/IJECE-V5I10P102

Research Article | Open Access

Volume 5 | Issue 10 | Year 2018 | Article Id. IJECE-V5I10P102 | DOI : https://doi.org/10.14445/23488549/IJECE-V5I10P102

Design of Low Power Encoder Using Switch Logic

Shaik Hameeda Noor, M.Venkata.Subbaiah, T.V.Nirmala, Dr.T.Lalith Kumar and S.Saleem

Citation :

Shaik Hameeda Noor, M.Venkata.Subbaiah, T.V.Nirmala, Dr.T.Lalith Kumar and S.Saleem, "Design of Low Power Encoder Using Switch Logic," International Journal of Electronics and Communication Engineering, vol. 5, no. 10, pp. 6-8, 2018. Crossref, https://doi.org/10.14445/23488549/IJECE-V5I10P102

Abstract

This document introduces a switch logic-design technique for line-encoders, including with transmission-gate-logic, pass-transistor-logic and standard complementary metal-oxide semi-conductor (CMOS).Targeting on reducing the transistor count t, power utilization All proposed encoders have full-voltage level capability and decreased transistor count considered with their standard CMOS methodology. Finally, a different types of simulation at 32 nm gives the present method gives a effective performance in power and delay.

Keywords

Encoder, Switch-Logic, PTL, and TG

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